(a) Field of the Invention
The present invention relates to a substrate having a capacitor embedded therein and, more particularly, to a capacitor-embedded substrate to be used as a base material for a multilayer wiring board or a module, or as an interposer, in each of which a semiconductor device (or chip), an electronic component or the like requiring high speed switching operation is mounted, and a method of manufacturing the same.
As employed herein, the multilayer wiring board is also referred to as a “semiconductor package” for the sake of convenience in the description below, in consideration of the function as a package for mounting semiconductor devices (or chips) or the like.
(b) Description of the Related Art
Semiconductor packages or the like have been recently required to have finer and denser wiring, and thus have been provided with wiring patterns in close proximity to each other. Such wiring patterns, however, can possibly cause a problem such as occurrence of crosstalk noise between wirings or variations in the potential of a power supply line or the like. In particular, in a package for mounting a semiconductor chip, an electronic component or the like required to perform high speed switching operation, the crosstalk noise is easy to be generated due to the rise in frequency, and also, high speed on-off operation of a switching element produces switching noise, so that variations in the potential of the power supply line or the like are easy to increase. To cope with this, packages for mounting semiconductor chips or the like have hitherto been provided with a chip capacitor for “decoupling” power supply lines or the like for the purposes of stabilization of power supply voltage and reduction in switching noises or the like.
However, this situation can possibly lead to the design freedom of the wiring pattern being restricted in accordance with the provision of the chip capacitor, or may possibly increase the routing length of the wiring pattern that connects the chip capacitor to a power supply/ground terminal of the semiconductor chip or the like, resulting in an increase in inductance. The smallest possible inductance is desirable because large inductance degreases a decoupling effect.
Instead of providing a chip capacitor to a package, other possible means for coping with the above problem is to provide an equivalent capacitative device inside a package. Also, the technologies of embedding a capacitor function into a substrate for passive components have come into practical use, accompanied by recent miniaturization and slimming-down of electronic devices such as mobile devices or portable devices. One of the technologies is to form a buried electrode in an insulating layer of the substrate by using a high-permittivity insulating sheet. In a typical configuration example of this technology, a high-permittivity insulating resin sheet (e.g., resin sheet containing an inorganic filler for enhancement of permittivity) is disposed as a dielectric of the capacitor in an organic resin substrate, and conductor layers (i.e., wiring layers) that form a pair of electrodes of the capacitor are provided on the resin sheet with being interposed therebetween.
One example of a technology related to the above conventional technology is disclosed in Japanese unexamined Patent Publication (Kokai) 2007-150180. The technology disclosed in this publication involves: providing at least one surface of a base material having flexibility with a wiring pattern; forming a circuit component monolithically integrated with the base material by filling a predetermined material into a groove formed in the one surface with a predetermined depth and in a predetermined pattern shape; and providing a connection between the circuit component and the wiring pattern, thereby forming a flexible circuit board. This flexible circuit board includes as one circuit component a capacitor constituted by: a pair of comb-shaped electrodes formed by filling an electrode material into grooves that are formed into comb-shaped patterns facing each other; and a dielectric layer formed by base material between the pair of comb-shaped electrodes.
As mentioned above, the technology of embedding the capacitor function into the semiconductor package has been brought into practical use accompanied by the recent miniaturization or the like of the electronic device and for the purposes of effective functioning of the decoupling effect. In this case, it is desirable that the capacitor have the largest possible capacitance in order to optimize the function as a capacitor. However, an attempt to increase the capacitance of the capacitor involves various problems as given below.
Specifically, a high-permittivity insulating resin sheet (with a permittivity about 45) as mentioned above has a considerably low value of the permittivity, compared with a conventionally-used ceramic chip capacitor (with a permittivity of about 20000). Therefore, considering the formation of the capacitor having larger capacitance (around 100 nF), achievement for the desired capacitance requires: an increase in size of the facing area of the electrodes having the sheet sandwiched therebetween; a reduction in thickness of the sheet (i.e., the distance between the electrodes); or a further heightening of the permittivity. To heighten the permittivity requires an increase in a content rate of the inorganic filler in the high-permittivity insulating resin sheet; however, there are technological limitations under the present circumstances. Meanwhile, as for the approach of reducing the thickness of the high-permittivity insulating resin sheet, the technology itself has its limitations for forming a thin resin sheet. Even if the sheet is successfully thinly formed in a desired thickness, the thinly formed sheet is fully expected to become difficult to handle.
On the other hand, the increase in size of the facing area of the electrodes (i.e., a portion of the conductor layer) having the high-permittivity insulating resin sheet sandwiched therebetween requires allocation of almost all portions of the conductor layers solely to the electrodes, which in turn increases the area occupied by the electrodes in the conductor layers and thus accordingly impairs the degree of freedom of other wirings. Another approach for the increase in size of the facing area of the electrodes is to alternately stack on top of each other the insulating layers (i.e., resin layers) that form the dielectrics, and the conductor layers that form the electrodes; however, it is required that the layers be formed one by one, as in the case of build-up process, which in turn increases the process time and hence leads to a rise in cost. Additionally, still another possible approach for the increase in size of the facing area of the electrodes is to form a staggered arrangement of the dielectrics (i.e., the insulating layers) and the electrodes (i.e., the conductor layers) to form a comb-shaped structure (namely, a parallel capacitor); however, with this approach, it is difficult to form a multilayer structure.